PPSC Computer Science Topic 17 MCQ's Test Preparation

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MCQ's Test For PPSC Computer Science Topic 17 Microprocessor And Assembly Language

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PPSC Computer Science Topic 17 Microprocessor And Assembly Language

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Question # 1

Which are the part of architecture of 8086

Question # 2

SP stand for

Question # 3

Who work as a cache for the page table.

Question # 4

The pin configuration of 8086 is available in the.

Question # 5

Which used to generate accurate time delays and can be used for other timing application such as a real time clock an event counter a digital one shot a square wave generator and a complex wave form generator.

Question # 6

The data in the stack is called.

Question # 7

A computer which has the microprocessor as ________ is called as a micro computer.

Question # 8

ED stand for

Question # 9

Which system communicates with the outside word via the I/O devices interfaced to it.

Question # 10

Which register is connected to the memory by way of the address bus.

Question # 11

Which generate an interrupt to the microprocessor after a certain interval of time.

Question # 12

CAD stand for.

Question # 13

Secondary memory can store.

Question # 14

Second level is a cache on the

Question # 15

AL 7 99H which operation is performed here

Question # 16

INT stand for

Question # 17

Power PC microprocessor architecture is developed by.

Question # 18

Which is the microprocessor comprises.

Question # 19

The time taken for all stages of the assembly line to become active is called the

Question # 20

Which processor provided 1 MB memory.

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Sr.# Question Answer
1 Using 12 binary digits how many queue house addresses would be possible.
A. 28 = 256
B. 212 = 4096
C. 216 = 65536
D. None
2 BP stand for
A. Bit pointer
B. Base pointer
C. Bus pointer
D. Byte pointer
3 How many micro processor in the market during the same period.
A. 3
B. 5
C. 6
D. 8
4 In which register instruction is decoded prepared and ultimately executed.
A. Instruction register
B. Current register
C. Both a and b
D. None
5 The principal of working of the cache memory largely depends on which locality.
A. Spatial locality
B. Temporal locality
C. Sequentially
D. All of these
6 The fetch execute cycle is to use a system know as.
A. Assembly line
B. Pipelining
C. Cache
D. None
7 How bit microprocessor inexpensive a separate interface is provided with I/O device.
A. 2 bit
B. 4 bit
C. 8 bit
D. 32 bit
8 Causing a flag to became 0 is called.
A. Clearing a flag
B. Case a flag
C. Both a and b
D. None
9 RD stand for
A. Read
B. Register
C. Request
D. Real
10 Which is designed is automatically manage the handshake operation.
A. 8251
B. 8254
C. 8255
D. 8259
11 WE stand for
A. Write enable
B. Wrote enable
C. Write envy
D. None
12 Who is the represents the fundamental process in the operation of the CPU
A. The fetch execute cycle and pipelining.
B. The assembly
C. Both a and b
D. None
13 In which form CPU provide output
A. Computer signals
B. Digital signals
C. Metal signals
D. None
14 The sub program finish the return instruction recovers the return address from the.
A. Queue
B. Stack
C. Program counter
D. Pointer
15 Micro processor is fabricated on single chip using.
A. MOS
B. ALU
C. CPU
D. All of these
16 The DMA controllers are special hardware embedded into the chip in modern integrate processor that __________ and ________ to the system.
A. Data transfer
B. Arbitrate access
C. Both a and b
D. None
17 The problems of bus confit and spares address distribution are eliminated by the use of ___ address technique.
A. Fully decoding
B. Half decoding
C. Both a and b
D. None
18 Which bus carry addresses
A. System bus
B. Address bus
C. Control bus
D. Data bus
19 ______is usually the first level of memory access by the microprocessor.
A. Cache memory
B. Data memory
C. Main memory
D. All of these
20 Which programmable timer is used to generate timing signal
A. 8255
B. 8254
C. 8251
D. 8259

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