PPSC Computer Science Topic 17 MCQ's Test Preparation

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MCQ's Test For PPSC Computer Science Topic 17 Microprocessor And Assembly Language

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PPSC Computer Science Topic 17 Microprocessor And Assembly Language

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Question # 1

Which Bus connects CPU and level 2 cache

Question # 2

The time taken for all stages of the assembly line to become active is called the

Question # 3

MOC stand for

Question # 4

L1 cache memory is places at

Question # 5

Which year intel family ensured.

Question # 6

_______ is the most commonly used cache controller with a number of processor sets.

Question # 7

Which is the components of microprocessor.

Question # 8

Each memory location has

Question # 9

Micro processor is the______ of computer.

Question # 10

The upper red arrow show that CPU sends out the control signals _____ and ____ indicate the data is read from the memory.

Question # 11

The external system bus architecture is created using from ______ architecture.

Question # 12

The four index register can be used for.

Question # 13

Which formula is used to calculate the number of write stall cycles.

Question # 14

They were fabricated using a low powered version of the HMOS technology called.

Question # 15

The mode of DMA are

Question # 16

34 H& AX which operation is performed here

Question # 17

A central processing unit fabricated on a single chip of semiconductor is called.

Question # 18

Which is the professional or Business version of intel processor.

Question # 19

VAM sand for

Question # 20

The fetch execute cycle is to use a system know as.

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Sr.# Question Answer
1 Secondary memory is also called.
A. Auxiliary
B. Backup store
C. Both a and b
D. None
2 DAC stand for
A. Analogue to analogue converters
B. Analogue to digital converters
C. Digital to digital converters
D. Digital to analogue converters
3 NMI stand for
A. Non mask able interrupt
B. Non mistake interrupt
C. Both a and b
D. None
4 Motorola has declined from having nearly __________ share of the microprocessor market to much smaller share.
A. 30%
B. 40%
C. 50%
D. 60%
5 The lower and bit are called.
A. AL
B. CL
C. BL
D. DL
6 Which is not the main feature of DEC alpha
A. 64 bit RISC processor
B. Designed to replace 32 VAX
C. Seven stage split integer point pipeline
D. Variable instruction length
7 In which register instruction is decoded prepared and ultimately executed.
A. Instruction register
B. Current register
C. Both a and b
D. None
8 The CPU removes the __________ signal to complete the memory write operation.
A. READ
B. WRITE
C. Both a and b
D. None
9 Which technology using the microprocessor is fabricated on single chip
A. POS
B. MOS
C. ALU
D. ABM
10 Which are the cache controller ports.
A. 64 bit AHB -Lite slave ports
B. 64- bit AHB -Lite Master ports
C. Both a and b
D. None
11 FIFO stand for.
A. First first other
B. First in first out
C. First in firs over
D. None
12 The external system bus architecture is created using from ______ architecture.
A. Pascal
B. Dennis Ritchie
C. Charles Babbage
D. Von Neumann
13 HLDA stand for
A. High acknowledgment
B. Hold acknowledgement
C. High access
D. Hold access
14 ___________ a sub system that transfer data between computer components inside a computer or between computer.
A. Chip
B. Register
C. Bus
D. processor
15 The mode of DMA are
A. Single transfer
B. Transfer
C. Repeated Sigel transfer
D. All of these
16 Which statement is false about WR signal
A. WR signal controls the input buffer
B. the bar over Wr means that this is an active low signal
C. the bar over WR means that this is an active high signal
D. If WR is 0 then the input data reaches the latch input.
17 HMOS stand for
A. High performance metal oxide semiconductor
B. High processor metal oxide semiconductor
C. Both a and b
D. None
18 ISR stand for
A. Interrupt service register
B. Input service register
C. In service register
D. All of these
19 The offset of a particular segment varies from_______
A. 000H to FFFH
B. 0000H to FFFFH
C. 00H to FFH
D. 00000H to FFFFFH
20 AEN stand for
A. Address enable
B. Address equivalent
C. Acknowledgment enable
D. Acknowledgment equivalent

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