PPSC Computer Science Topic 17 MCQ's Test Preparation

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MCQ's Test For PPSC Computer Science Topic 17 Microprocessor And Assembly Language

Try The MCQ's Test For PPSC Computer Science Topic 17 Microprocessor And Assembly Language

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PPSC Computer Science Topic 17 Microprocessor And Assembly Language

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Question # 1

L2 cache memory is places at __________

Question # 2

The processer of knowing the status of device and transferring the data with matching speeds is called.

Question # 3

Which is not the open source OS.

Question # 4

Customized ROMS are called.

Question # 5

Which multiplex by ADC 0808/0809

Question # 6

The point where control returns after a subprogram is completed is known as the.

Question # 7

A nibble can be represented in the from of.

Question # 8

Which is the types of cache memory

Question # 9

The amount of information which can be plead at one time in the cache memory is called.

Question # 10

Which programmable timer is used to generate timing signal

Question # 11

AL 7 99H which operation is performed here

Question # 12

MAR stand for

Question # 13

Which formula is used to calculate the number of read stall cycles.

Question # 14

Direct mapping is a _____________ to implement cache memory

Question # 15

How bit microprocessor inexpensive a separate interface is provided with I/O device.

Question # 16

Which formula is used to calculate the number of write stall cycles.

Question # 17

The range of this rating for which microprocessor of.

Question # 18

The DMA controllers are specials hardware embedded into the chip in modern integrate processor that ____________ and _________ to the system.

Question # 19

Which is designed is automatically manage the handshake operation.

Question # 20

______is usually the first level of memory access by the microprocessor.

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PPSC ComputerScience Chapter 17 Important MCQ's

Sr.# Question Answer
1 The DMA controllers are specials hardware embedded into the chip in modern integrate processor that ____________ and _________ to the system.
A. Data transfer
B. Arbitrate access
C. Both a and b
D. None
2 The offset of a particular segment varies from_______
A. 000H to FFFH
B. 0000H to FFFFH
C. 00H to FFH
D. 00000H to FFFFFH
3 The time taken for all stages of the assembly line to become active is called the
A. Flow through time
B. Clock period
C. Through put
D. All of these
4 How many bit or MAR register
A. 8 bit
B. 16 bit
C. 32 bit
D. 64 bit
5 RD stand for
A. Read
B. Register
C. Request
D. Real
6 Which technology using the microprocessor is fabricated on single chip
A. POS
B. MOS
C. ALU
D. ABM
7 WE stand for
A. Write enable
B. Wrote enable
C. Write envy
D. None
8 The capacity of this chip is 1 KB they are organized in the form of 1024 words with 8 bit word the what is the site of address bus.
A. 8 bit
B. 10 bit
C. 12 bit
D. 16 bit
9 MOS stand for
A. Metal oxide semiconductor
B. Memory oxide semiconductor
C. Metal oxide select
D. None
10 There are primarily two types of register
A. General purpose register
B. Dedicated register
C. a and b
D. None

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