VU CS-302 Online Test Preparation

MCQ's Test For CS-302 Quiz Preparation Virtual University

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CS-302 Quiz Preparation Virtual University

00:00
Question # 1

In asynchronous transmission when the transmission line is idle, _________

Question # 2

FIFO is an acronym for __________

Question # 3

A GAL is essentially a ________.

Question # 4

When the control line in tri-state buffer is high the buffer operates like a ________gate

Question # 5

We have a digital circuit. Different parts of circuit operate at different clock frequencies (4MHZ, 2MHZ and 1MHZ), but we have a single clock source having a fix clock frequency (4MHZ), we can get help by ___________

Question # 6

Sum term (Max term) is implemented using ________ gates

Question # 7

The output of the expression F=A.B.C will be Logic ________ when A=1, B=0, C=1

Question # 8

The OR Gate performs a Boolean _______ function

Question # 9

In ________ outputs depend only on the current state

Question # 10

(A + B)(A + B + C)(A + C) is an example of ______________

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Virtual University CS-302 Chapter 1 Important MCQ's

Sr.# Question Answer
1 ____________ counters as the name indicates are not triggered simultaneously.
A. Asynchronous
B. Synchronous
C. Positive-Edge triggered
D. Negative-Edge triggered
2 Determine the values of A, B, C, and D that make the sum term A(bar) + B+C(bar)+D equal to zero.
A. A = 1, B = 0, C = 0, D = 0
B. A = 1, B = 0, C = 1, D = 0
C. A = 0, B = 1, C = 0, D = 0
D. A = 1, B = 0, C = 1, D = 1
3
The output of an XNOR gate is 1 when ____________ . I) All the inputs are zero II) Any of the inputs is zero III) Any of the inputs is one IV) All the inputs are one.
A. I Only
B. IV Only
C. I and IV only
D. II and III only
4 Caveman number system is Base ______ number system
A. 2
B. 5
C. 10
D. 16
5 A Nibble consists of _____ bits
A. 2
B. 8
C. 4
D. 16
6 If the FIFO Memory output is already filled with data then ________
A. It is locked; no data is allowed to enter
B. It is not locked; the new data overwrites the previous data.
C. Previous data is swapped out of memory and new data enters
D. None of given options
7 A 8-bit serial in / parallel out shift register contains the value “8”, _____ clock signal(s) will be required to shift the value completely out of the register.
A. 1
B. 2
C. 4
D. 8
8 A GAL is essentially a ________.
A. Non-reprogrammable PAL
B. PAL that is programmed only by the manufacturer
C. Very large PAL
D. Reprogrammable PAL
9 In a state diagram, the transition from a current state to the next state is determined by.
A. Current state and the inputs
B. Current state and outputs
C. Previous state and inputs
D. Previous state and outputs
10 The operation of J-K flip-flop is similar to that of the SR flip-flop except that the J-K flip-flop ___________
A. Doesn’t have an invalid state
B. Sets to clear when both J = 0 and K = 0
C. It does not show transition on change in pulse
D. It does not accept asynchronous inputs

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