VU CS-302 Online Test Preparation

MCQ's Test For CS-302 Quiz Preparation Virtual University

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CS-302 Quiz Preparation Virtual University

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Question # 1

For a gated D-Latch if EN=1 and D=1 then Q(t+1) = _________

Question # 2

THE GLITCHES DUE TO RACE CONDITION CAN BE AVOIDED BY USING A ___________

Question # 3

The simplest and most commonly used Decoders are the ______ Decoders

Question # 4

NAND gate is formed by connecting _________

Question # 5

The alternate solution for a multiplexer and a register circuit is _________

Question # 6

The design and implementation of synchronous counters start from _________

Question # 7

The operation of J-K flip-flop is similar to that of the SR flip-flop except that the J-K flip-flop ___________

Question # 8

Above is the circuit diagram of _______.

Question # 9

An alternate method of implementing Comparators which allows the Comparators to be easily cascaded without the need for extra logic gates is _______

Question # 10

The output of the expression F=A.B.C will be Logic ________ when A=1, B=0, C=1

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Virtual University CS-302 Chapter 1 Important MCQ's

Sr.# Question Answer
1 Consider an up/down counter that counts between 0 and 15, if external input(X) is “0” the counter counts upward (0000 to 1111) and if external input (X) is “1” the counter counts downward (1111 to 0000), now suppose that the present state is “1100” and X=1, the next state of the counter will be ___________
A. 0000
B. 1101
C. 1011
D. 1111
2 The divide-by-60 counter in digital clock is implemented by using two cascading counters
A. Mod-6, Mod-10
B. Mod-50, Mod-10
C. Mod-10, Mod-50
D. Mod-50, Mod-6
3 5-bit Johnson counter sequences through ____ states
A. 7
B. 10
C. 32
D. 25
4 The low to high or high to low transition of the clock is considered to be a(n) ________.
A. State
B. Edge
C. Trigger
D. One-shot
5 RCO Stands for _________
A. Reconfiguration Counter Output
B. Reconfiguration Clock Output
C. Ripple Counter Output
D. Ripple Clock Output
6 Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble 1100. What will be the 4-bit pattern after the second clock pulse? (Right-most bit first.)
A. 1100
B. 0011
C. 0000
D. 1111
7 The alternate solution for a multiplexer and a register circuit is _________
A. Parallel in / Serial out shift register
B. Serial in / Parallel out shift register
C. Parallel in / Parallel out shift register
D. Serial in / Serial Out shift register
8 A counter is implemented using three (3) flip-flops, possibly it will have ________ maximum output status
A. 3
B. 7
C. 8
D. 15
9 74HC163 has two enable input pins which are _______ and _________
A. ENP, ENT
B. ENI, ENC
C. ENP, ENC
D. ENT, ENI
10
________ is used to minimize the possible no. of states of a circuit.
A. State assignment
B. State reduction
C. Next state table
D. State diagram

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