VU CS-302 Online Test Preparation

MCQ's Test For CS-302 Quiz Preparation Virtual University

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CS-302 Quiz Preparation Virtual University

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Question # 1

74HC163 has two enable input pins which are _______ and _________

Question # 2

A frequency counter ______________

Question # 3

74HC163 has two enable input pins which are _______ and _________

Question # 4

In a sequential circuit the next state is determined by ________ and _______

Question # 5

The output of the expression F=A.B.C will be Logic ________ when A=1, B=0, C=1

Question # 6

In a state diagram, the transition from a current state to the next state is determined by

Question # 7

We have a digital circuit. Different parts of circuit operate at different clock frequencies (4MHZ, 2MHZ and 1MHZ), but we have a single clock source having a fix clock frequency (4MHZ), we can get help by ___________

Question # 8

The expression F=A+B+C describes the operation of three bits _____ Gate

Question # 9

The divide-by-60 counter in digital clock is implemented by using two cascading counters

Question # 10

A multiplexer with a register circuit converts _________

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Virtual University CS-302 Chapter 1 Important MCQ's

Sr.# Question Answer
1 A counter is implemented using three (3) flip-flops, possibly it will have ________ maximum output status
A. 3
B. 7
C. 8
D. 15
2 A synchronous decade counter will have _______ flip-flops
A. 3
B. 4
C. 7
D. 10
3 Stack is an acronym for _________
A. FIFO memory
B. LIFO memory
C. Flash Memory
D. Bust Flash Memory
4 In the following statement Z PIN 20 ISTYPE „reg.invert‟; The keyword “reg.invert” indicates ________
A. An inverted register input
B. An inverted register input at pin 20
C. Active-high Registered Mode output
D. Active-low Registered Mode output
5 A frequency counter ______________
A. Counts pulse width
B. Counts no. of clock pulses in 1 second
C. Counts high and low range of given clock pulse
D. None of given options
6 LUT is acronym for _________
A. Look Up Table
B. Local User Terminal
C. Least Upper Time Period
D. None of given options
7 Consider an up/down counter that counts between 0 and 15, if external input(X) is “0” the counter counts upward (0000 to 1111) and if external input (X) is “1” the counter counts downward (1111 to 0000), now suppose that the present state is “1100” and X=1, the next state of the counter will be ___________
A. 0000
B. 1101
C. 1011
D. 1111
8 The design and implementation of synchronous counters start from _________
A. Truth table
B. state diagram
C. k-map
D. state table
9 A multiplexer with a register circuit converts _________
A. Serial data to parallel
B. Parallel data to serial
C. Serial data to serial
D. Parallel data to parallel
10 The design and implementation of synchronous counters start from _________
A. state table
B. k-map
C. state diagram
D. Truth table

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