PPSC Computer Science Full Book test With Answers

PPSC Computer Science Full Book test

Sr. # Questions Answers Choice
1 IRR stand for Interrupt request register Input request register Input resolver register Interrupt resolver register
2 EOC stand for End of conversion Emphasize of conversion End of controller None
3 INTR it implies the ___ signal Interrupt request Interrupt Right Interrupt Rough interrupt Reset
4 Which is responsible for all the outside world communication by the microprocessor. BIU PIU TIU LIU
5 Cache can be controlled. 16 KB - 2MB 17 KB - 2MB 18 KB - 2 MB 19 KB - 2MB
6 Which are the cache controller ports. 64 bit AHB -Lite slave ports 64- bit AHB -Lite Master ports Both a and b None
7 Which causes the microprocessor to immediately terminate its present activity. RESET Signal INTERUPT signal Both None
8 Which formula is used to calculate the number of write stall cycles. Reads * read miss rate* read miss penalty write * write miss + Write buffer stalls Memory access* cache miss rate * cache miss penalty None
9 Which formula is used to calculate the number of read stall cycles. None Reads read miss rate read miss penalty Write +Wrier buffer stalls Memory access* cache miss rate * cache miss penalty
10 Who work as a cache for the page table. TLB TLP LEB WAB
11 The principal of working of the cache memory largely depends on which locality. Spatial locality Temporal locality Sequentially All of these
12 Cache is usually the ______ of memory access by the microprocessor. First level Second level Third level Fourth level
13 The memory system is said to be effective if the access time of the cache is close to the effective access time of the. ROM RAM HDD Processor
14 Second level is a cache on the Main memory RAM Both a and b None
15 Who works as cache on the variable. Memory Pointer Register Segment
16 The parity bits are used to check that a. Two bit error Single bit error Multi bit error None
17 The index high order bits in the address known as. Tags label Point Location
18 Inc case of direct mapped cache lower order line address bits are used the access the RAM ROM Directory HDD
19 WA Stand for Write allocate Wrote allocate Way allocate Word allocate
20 WB stand for Write buffers Written buffers Wrote buffers None
21 EB stand for Effect buffers Effecting buffers Effect ion buffers Eviction buffers
22 LRB stand for Line ready buffers Line root buffers Line read buffers Line right buffers
23 LFB stand for Line full buffers Line fill buffers Line fan buffers None
24 _______ is the most commonly used cache controller with a number of processor sets. L 211 controller L 210 controller L 214 controller None
25 Microprocessor reference that are available in the cache are called. Cache hits Cache line Cache misses Cache memory
26 FIFO stand for. First first other First in first out First in firs over None
27 A fourth bit called the Direct bit Cache bit Valid bit All of these
28 Direct mapping is a _____________ to implement cache memory Cheaper way Case way Cache way None
29 Which memory is used to holds the address of the data stored in the cache. Associative memory Case memory Ordinary memory None
30 Which is the types of cache memory Fully associative cache Direct mapped cache Set associative cache All of these
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