PPSC Computer Science Chapter 17 Microprocessor And Assembly Language Online Test With Answers

PPSC Computer Science Chapter 17 Microprocessor And Assembly Language Online Test

Sr. # Questions Answers Choice
1 Who is the Brian of computer ALU CPU MU None
2 PC's use_______ based on this architecture. CPU ALU MU None
3 CISC stand for Complex instruction set computer Computer instruct set of computer Compared instruction set computer None
4 Which are the architectural paradigms in microprocessor. RISC CISC PISC A and B
5 How many architectural paradigms in microprocessor. 2 3 4 6
6 DEC stand for Digital electronic computer Digital electronic corporation Digital equipment corporation None
7 RISC stand for. Reduced instruction set computer Reduced instruct set compare Reduce instruction stand computer All of these
8 ISA stand for Instruct set area Instruction set architecture Both a and b None
9 Which is not the open source OS. Debian BSD unix Gentoo and Red Hat Linux Windows
10 Which is not the main feature of DEC alpha 64 bit RISC processor Designed to replace 32 VAX Seven stage split integer point pipeline Variable instruction length
11 Alpha AXP is developed by DEC IBM Motorola Intel
12 Which is not the main architectural feature of Power PC. It is not based on RISC Superscalar implementation Both 32 and 64 bit Paged memory managemnet architecture
13 Power PC microprocessor architecture is developed by. Apple IBM Motorola All these
14 What is the maximum clock speed of PIII processor. 1.0 GHz 1.1 GHz 1.2 GHz 1.3 GHz
15 Pentium III processor is released in the form of. Socket 370 version Slot 1 version in plastic cartridge Both a and b None
16 Which is the professional or Business version of intel processor. Pentium II Pentium pro Pentium MMX Pentium Xeon
17 Pentium pro can address______ of memory. 4 GB 128 GB 256 GB 512 GB
18 L2 cache memory is places at __________ On processor On mother board On memory All of these
19 L1 cache memory is places at On processor On mother board On memory All of these
20 Pentium pro processor contains L1 Cache L2 cache Both a and b None
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