Question # 1

A synchronous decade counter will have _______ flip-flops.

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3

4

7

10

A positive edge-triggered flip-flop changes its state when ________________

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Low-to-high transition of clock

High-to-low transition of clock

Enable input (EN) is set

Preset input (PRE) is set

In asynchronous transmission when the transmission line is idle, _________

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It is set to logic low

Remains in previous state

It is set to logic high

State of transmission line is not used to start transmission

At T0 the value stored in a 4-bit left shift was “1”. What will be the value of register after three clock pulses?

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2

4

6

8

A Nibble consists of _____ bits

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2

8

4

16

The _________ of a ROM is the time it takes for the data to appear at the Data Output of the ROM chip after an address is applied at the address input lines.

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Write Time

Recycle Time

Refresh Time

Access Time

A flip-flop is connected to +5 volts and it draws 5 mA of current during its operation, the power dissipation of the flip-flop is

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10 mW

25 mW

64 mW

1024

A divide-by-50 counter divides the input ______ signal to a 1 Hz signal.

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10 Hz

50 Hz

100 Hz

500 Hz

A GAL is essentially a ________.

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Non-reprogrammable PAL

PAL that is programmed only by the manufacturer

Very large PAL

Reprogrammable PAL

A multiplexer with a register circuit converts _________

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Serial data to parallel

Parallel data to serial

Serial data to serial

Parallel data to parallel

The binary numbers A = 1100 and B = 1001 are applied to the inputs of a comparator. What are the output levels?

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A > B = 1, A < B = 0, A < B = 1

A > B = 0, A < B = 1, A = B = 0

A > B = 1, A < B = 0, A = B = 0

A > B = 0, A < B = 1, A = B = 1

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