Question # 1

Consider A=1,B=0,C=1. A, B and C represent the input of three bit NAND gate the output of the NAND gate will be _____

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Zero

One

Undefined

No output as input is invalid

in ____________, all the columns in the same row are either read or written.

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Sequential Access

MOS Access

FAST Mode Page Access

None of given options

The divide-by-60 counter in digital clock is implemented by using two cascading counters:

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Mod-6, Mod-10

Mod-50, Mod-10

Mod-10, Mod-50

Mod-50, Mod-6

In _______ the Q output of the last flip-flop of the shift register is connected to the data input of the first flipflop.

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Moore machine

Meally machine

Johnson counter

Ring counter

FIFO is an acronym for __________

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First In, First Out

Fly in, Fly Out

Fast in, Fast Out

None of given options

LUT is acronym for _________.

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Look Up Table

Local User Terminal

Least Upper Time Period

None of given options

A multiplexer with a register circuit converts _________

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Serial data to parallel

Parallel data to serial

Serial data to serial

Parallel data to parallel

A positive edge-triggered flip-flop changes its state when ________________

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Low-to-high transition of clock

High-to-low transition of clock

Enable input (EN) is set

Preset input (PRE) is set

Demultiplexer converts _______ data to __________ data.

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Parallel data, serial data

Serial data, parallel data

Encoded data, decoded data

All of the given options

"A + B = B + A" is __________

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Demorgan‟s Law

Distributive Law

Commutative Law

Associative Law

A logic circuit with an output consists of ________

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two AND gates, two OR gates, two inverters

three AND gates, two OR gates, one inverter

two AND gates, one OR gate, two inverters

two AND gates, one OR gate

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