Question # 1

The minimum time for which the input signal has to be maintained at the input of flip-flop is called ______ of the flip-flop.

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Set-up time

Hold time

Pulse Interval time

Pulse Stability time

What is the difference between a D latch and a D flip-flop?

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The D latch has a clock input

The D flip-flop has an enable input

The D latch is used for faster operation

The D flip-flop has a clock input

Generally, the Power dissipation of _______ devices remains constant throughout their operation.

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TTL

CMOS 3.5 series

CMOS 5 Series

Power dissipation of all circuits increases with time

A frequency counter ______________

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Counts pulse width

Counts no. of clock pulses in 1 second

Counts high and low range of given clock pulse

None of given options

Excess-8 code assigns _______ to “+7”

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0000

1001

1000

1111

A GAL is essentially a ________.

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Non-reprogrammable PAL

PAL that is programmed only by the manufacturer

Very large PAL

Reprogrammable PAL

3.3 v CMOS series is characterized by __________ and _________as compared to the 5 v CMOS series

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Low switching speeds, high power dissipation

Fast switching speeds, high power dissipation

Fast switching speeds, very low power dissipation

Low switching speeds, very low power dissipation

NOR gate is formed by connecting _________

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OR Gate and then NOT Gate

NOT Gate and then OR Gate

AND Gate and then OR Gate

OR Gate and then AND Gate

A negative edge-triggered flip-flop changes its state when ________________

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Enable input (EN) is set

Preset input (PRE) is set

Low-to-high transition of clock

High-to-low transition of clock

________ is used to minimize the possible no. of states of a circuit.

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State assignment

State reduction

Next state table

State diagram

The simplest and most commonly used Decoders are the ______ Decoders

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n to 2n

(n-1) to 2n

(n-1) to (2n-1)

n to 2n-1

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