Question # 1

________ is used to simplify the circuit that determines the next state.

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State diagram

Next state table

State reduction

State assignment

The alternate solution for a demultiplexer-register combination circuit is _________

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Parallel in / Serial out shift register

Serial in / Parallel out shift register

Parallel in / Parallel out shift register

Serial in / Serial Out shift register

The operation of J-K flip-flop is similar to that of the SR flip-flop except that the J-K flip-flop ___________

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Doesn’t have an invalid state

Sets to clear when both J = 0 and K = 0

It does not show transition on change in pulse

It does not accept asynchronous inputs

The output of an XOR gate is zero (0) when __________ I) All the inputs are zero II) Any of the inputs is zero III) Any of the inputs is one IV) All the inputs are one.

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I Only

IV Only

I and IV only

II and III only

We have a digital circuit. Different parts of circuit operate at different clock frequencies (4MHZ, 2MHZ and 1MHZ), but we have a single clock source having a fix clock frequency (4MHZ), we can get help by ___________

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Using S-R Flop-Flop

D-flipflop

J-K flip-flop

T-Flip-Flop

Consider A=1,B=0,C=1. A, B and C represent the input of three bit NAND gate the output of the NAND gate will be _____

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Zero

One

Undefined

No output as input is invalid

The best state assignment tends to ___________.

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Maximizes the number of state variables that don’t change in a group of related states

Minimizes the number of state variables that don‟t change in a group of related states

Minimize the equivalent states

None of given options

The storage cell in SRAM is

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a flip –flop

a capacitor

a fuse

a magnetic domain

(A + B)(A + B + C)(A + C) is an example of ______________

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Product of sum form

Sum of product form

Demorgans law

Associative law

The expression F=A+B+C describes the operation of three bits _____ Gate

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OR

AND

NOT

NAND

________ is used to minimize the possible no. of states of a circuit.

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State assignment

State reduction

Next state table

State diagram

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