Question # 1

The divide-by-60 counter in digital clock is implemented by using two cascading counters

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Mod-6, Mod-10

Mod-50, Mod-10

Mod-10, Mod-50

Mod-50, Mod-6

The _______ Encoder is used as a keypad encoder.

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2-to-8 encoder

4-to-16 encoder

BCD-to-Decimal

Decimal-to-BCD Priority

In designing any counter the transition from a current state to the next sate is determined by

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Current state and inputs

Only inputs

Only current state

current state and outputs

The OR gate performs Boolean ___________.

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multiplication

subtraction

division

addition

Bi-stable devices remain in either of their _________ states unless the inputs force the device to switch its state

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Ten

Eight

Three

Two

If the S and R inputs of the gated S-R latch are connected together using a ______gate then there is only a single input to the latch. The input is represented by D instead of S or R (A gated D-Latch)

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AND

OR

NOT

XOR

Q2 :=Q1 OR X OR Q3 The above ABEL expression will be

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Q2:= Q1 $ X $ Q3

Q2:= Q1 # X # Q3

Q2:= Q1 & X & Q3

Q2:= Q1 ! X ! Q3

A negative edge-triggered flip-flop changes its state when ________________

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Enable input (EN) is set

Preset input (PRE) is set

Low-to-high transition of clock

High-to-low transition of clock

The output of an XNOR gate is 1 when ____________ . I) All the inputs are zero II) Any of the inputs is zero III) Any of the inputs is one IV) All the inputs are one.

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I Only

IV Only

I and IV only

II and III only

If S=1 and R=0, then Q(t+1) = _________ for positive edge triggered flip-flop

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0

1

Invalid

Input is invalid

________ is used to simplify the circuit that determines the next state.

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State diagram

Next state table

State reduction

State assignment

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