Question # 1

The PROM consists of a fixed non-programmable ____________ Gate array configured as a decoder

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AND

OR

NOT

XOR

A positive edge-triggered flip-flop changes its state when ________________

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Low-to-high transition of clock

High-to-low transition of clock

Enable input (EN) is set

Preset input (PRE) is set

Excess-8 code assigns _______ to “+7”

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0000

1001

1000

1111

In a sequential circuit the next state is determined by ________ and _______.

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State variable, current state

Current state, flip-flop output

Current state and external input

Input and clock signal applied

The output of the expression F=A.B.C will be Logic ________ when A=1, B=0, C=1

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Undefined

One

Zero

No Output as input is invalid

If an S-R latch has a 1 on the S input and a 0 on the R input and then the S input goes to 0, the latch will be

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set

reset

invalid

clear

___________ is one of the examples of synchronous inputs

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J-K input

EN input

Preset input (PRE)

Clear Input (CLR)

Which is not characteristic of a shift register?

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Serial in/parallel in

Serial in/parallel out

Parallel in/serial out

Parallel in/parallel out

Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble 1100. What will be the 4-bit pattern after the second clock pulse? (Right-most bit first.)

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1100

0011

0000

1111

The _______ Encoder is used as a keypad encoder.

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2-to-8 encoder

4-to-16 encoder

BCD-to-Decimal

Decimal-to-BCD Priority

The operation of J-K flip-flop is similar to that of the SR flip-flop except that the J-K flip-flop ___________

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Doesn’t have an invalid state

Sets to clear when both J = 0 and K = 0

It does not show transition on change in pulse

It does not accept asynchronous inputs

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