Question # 1

"A + B = B + A" is __________

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Demorgan‟s Law

Distributive Law

Commutative Law

Associative Law

The basic building block for a logical circuit is _______

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A Flip-Flop

A Logical Gate

An Adder

None of given options

A multiplexer with a register circuit converts _________

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Serial data to parallel

Parallel data to serial

Serial data to serial

Parallel data to parallel

If S=1 and R=1, then Q(t+1) = _________ for negative edge triggered flip-flop

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0

1

Invalid

Input is invalid

A logic circuit with an output consists of ________

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two AND gates, two OR gates, two inverters

three AND gates, two OR gates, one inverter

two AND gates, one OR gate, two inverters

two AND gates, one OR gate

If the FIFO Memory output is already filled with data then ________

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It is locked; no data is allowed to enter

It is not locked; the new data overwrites the previous data.

Previous data is swapped out of memory and new data enters

None of given options

The PROM consists of a fixed non-programmable ____________ Gate array configured as a decoder

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AND

OR

NOT

XOR

____________ is said to occur when multiple internal variables change due to change in one input variable.

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Clock Skew

Race condition

Hold delay

Hold and Wait

In ________ outputs depend only on the combination of current state and inputs.

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Mealy machine

Moore Machine

State Reduction table

State Assignment table

FIFO is an acronym for __________

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First In, First Out

Fly in, Fly Out

Fast in, Fast Out

None of given options

In order to synchronize two devices that consume and produce data at different rates, we can use _________

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Read Only Memory

Fist In First Out Memory

Flash Memory

Fast Page Access Mode Memory

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