Question # 1

________ is invalid number of cells in a single group formed by the adjacent cells in K-map

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2

8

12

16

If the FIFO Memory output is already filled with data then ________

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It is locked; no data is allowed to enter

It is not locked; the new data overwrites the previous data.

Previous data is swapped out of memory and new data enters

None of given options

The simplest and most commonly used Decoders are the ______ Decoders

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n to 2n

(n-1) to 2n

(n-1) to (2n-1)

n to 2n-1

In _______ the Q output of the last flip-flop of the shift register is connected to the data input of the first flipflop.

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Moore machine

Meally machine

Johnson counter

Ring counter

The total amount of memory that is supported by any digital system depends upon ______

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The organization of memory

The structure of memory

The size of decoding unit

The size of the address bus of the microprocessor

THE GLITCHES DUE TO RACE CONDITION CAN BE AVOIDED BY USING A ___________

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GATED FLIP-FLOPS

PULSE TRIGGERED FLIP-FLOPS

POSITIVE-EDGE TRIGGERED FLIP-FLOPS

NEGATIVE-EDGE TRIGGERED FLIP-FLOPS

A positive edge-triggered flip-flop changes its state when ________________

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Low-to-high transition of clock

High-to-low transition of clock

Enable input (EN) is set

Preset input (PRE) is set

________ is used to simplify the circuit that determines the next state.

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State diagram

Next state table

State reduction

State assignment

Q2 :=Q1 OR X OR Q3

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Q2:= Q1 $ X $ Q3

Q2:= Q1 # X # Q3

Q2:= Q1 & X & Q3

Q2:= Q1 ! X ! Q3

3.3 v CMOS series is characterized by __________ and _________as compared to the 5 v CMOS series

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Low switching speeds, high power dissipation

Fast switching speeds, high power dissipation

Fast switching speeds, very low power dissipation

Low switching speeds, very low power dissipation

A 8-bit serial in / parallel out shift register contains the value “8”, _____ clock signal(s) will be required to shift the value completely out of the register.

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1

2

4

8

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