Question # 1

________ is used to minimize the possible no. of states of a circuit.

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State assignment

State reduction

Next state table

State diagram

Stack is an acronym for _________

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FIFO memory

LIFO memory

Flash Memory

Bust Flash Memory

Above is the circuit diagram of _______.

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Asynchronous up-counter

Asynchronous down-counter

Synchronous up-counter

Synchronous down-counter

The 3-variable Karnaugh Map (K-Map) has _______ cells for min or max terms

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4

8

12

16

Determine the values of A, B, C, and D that make the sum term A(bar) + B+C(bar)+D equal to zero.

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A = 1, B = 0, C = 0, D = 0

A = 1, B = 0, C = 1, D = 0

A = 0, B = 1, C = 0, D = 0

A = 1, B = 0, C = 1, D = 1

The process of converting the analogue signal into a digital representation (code) is known as ___________

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Strobing

Amplification

Quantization

Digitization

The decimal “17” in BCD will be represented as _________

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₁₁₁₀₁

11011

10111

11110

A transparent mode means _____________.

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The changes in the data at the inputs of the latch are seen at the output

The changes in the data at the inputs of the latch are not seen at the output

Propagation Delay is zero (Output is immediately changed when clock signal is applied)

Input Hold time is zero (no need to maintain input after clock transition)

The binary numbers A = 1100 and B = 1001 are applied to the inputs of a comparator. What are the output levels?

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A > B = 1, A < B = 0, A < B = 1

A > B = 0, A < B = 1, A = B = 0

A > B = 1, A < B = 0, A = B = 0

A > B = 0, A < B = 1, A = B = 1

The divide-by-60 counter in digital clock is implemented by using two cascading counters

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Mod-6, Mod-10

Mod-50, Mod-10

Mod-10, Mod-50

Mod-50, Mod-6

The minimum time for which the input signal has to be maintained at the input of flip-flop is called ______ of the flip-flop.

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Set-up time

Hold time

Pulse Interval time

Pulse Stability time

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