Question # 1

The divide-by-60 counter in digital clock is implemented by using two cascading counters

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Mod-6, Mod-10

Mod-50, Mod-10

Mod-10, Mod-50

Mod-50, Mod-6

Consider A=1,B=0,C=1. A, B and C represent the input of three bit NAND gate the output of the NAND gate will be _____

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Zero

One

Undefined

No output as input is invalid

NAND gate is formed by connecting _________

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AND Gate and then NOT Gate

NOT Gate and then AND Gate

AND Gate and then OR Gate

OR Gate and then AND Gate

The minimum time for which the input signal has to be maintained at the input of flip-flop is called ______ of the flip-flop.

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Set-up time

Hold time

Pulse Interval time

Pulse Stability time

74HC163 has two enable input pins which are _______ and _________.

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ENP, ENT

ENI, ENC

ENP, ENC

ENT, ENI

THE GLITCHES DUE TO RACE CONDITION CAN BE AVOIDED BY USING A ___________

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GATED FLIP-FLOPS

PULSE TRIGGERED FLIP-FLOPS

POSITIVE-EDGE TRIGGERED FLIP-FLOPS

NEGATIVE-EDGE TRIGGERED FLIP-FLOPS

RCO Stands for _________

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Reconfiguration Counter Output

Reconfiguration Clock Output

Ripple Counter Output

Ripple Clock Output

Caveman number system is Base ______ number system

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2

5

10

16

(A + B)(A + B + C)(A + C) is an example of ______________

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Product of sum form

Sum of product form

Demorgans law

Associative law

A frequency counter ______________

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Counts pulse width

Counts no. of clock pulses in 1 second

Counts high and low range of given clock pulse

None of given options

Sum term (Max term) is implemented using ________ gates

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OR

AND

NOT

OR-AND

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