Question # 1

For a positive edge-triggered J-K flip-flop with both J and K HIGH, the outputs will______ if the clock goes HIGH

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toggle

set

reset

not change

The output of an AND gate is one when _______

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All of the inputs are one

Any of the input is one

Any of the input is zero

All the inputs are zero

The decimal “17” in BCD will be represented as _________10001(right opt is not given)

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11101

10111

11110

Sum term (Max term) is implemented using ________ gates

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OR

AND

NOT

OR-AND

Above is the circuit diagram of _______.

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Asynchronous up-counter

Asynchronous down-counter

Synchronous up-counter

Synchronous down-counter

Excess-8 code assigns _______ to “-8”

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1110

1100

1000

0000

3.3 v CMOS series is characterized by __________ and _________as compared to the 5 v CMOS series

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Low switching speeds, high power dissipation

Fast switching speeds, high power dissipation

Fast switching speeds, very low power dissipation

Low switching speeds, very low power dissipation

The power dissipation, PD, of a logic gate is the product of the

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dc supply voltage and the peak current

dc supply voltage and the average supply current

ac supply voltage and the peak current

ac supply voltage and the average supply current

In ________ outputs depend only on the combination of current state and inputs.

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Mealy machine

Moore Machine

State Reduction table

State Assignment table

In the following statement Z PIN 20 ISTYPE „reg.invert‟; The keyword “reg.invert” indicates ________

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An inverted register input

An inverted register input at pin 20

Active-high Registered Mode output

Active-low Registered Mode output

FIFO is an acronym for __________

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First In, First Out

Fly in, Fly Out

Fast in, Fast Out

None of given options

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