Question # 1

If S=1 and R=1, then Q(t+1) = _________ for negative edge triggered flip-flop

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0

1

Invalid

Input is invalid

Bi-stable devices remain in either of their _________ states unless the inputs force the device to switch its state

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Ten

Eight

Three

Two

The address from which the data is read, is provided by _______

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Depends on circuitry

None of given options

RAM

Microprocessor

A negative edge-triggered flip-flop changes its state when ________________

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Enable input (EN) is set

Preset input (PRE) is set

Low-to-high transition of clock

High-to-low transition of clock

LUT is acronym for _________.

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Look Up Table

Local User Terminal

Least Upper Time Period

None of given options

The PROM consists of a fixed non-programmable ____________ Gate array configured as a decoder

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AND

OR

NOT

XOR

In asynchronous transmission when the transmission line is idle, _________

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It is set to logic low

It is set to logic high

Remains in previous state

State of transmission line is not used to start transmission

The _________ of a ROM is the time it takes for the data to appear at the Data Output of the ROM chip after an address is applied at the address input lines.

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Write Time

Recycle Time

Refresh Time

Access Time

The total amount of memory that is supported by any digital system depends upon ______

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The organization of memory

The structure of memory

The size of decoding unit

The size of the address bus of the microprocessor

___________ is one of the examples of synchronous inputs.

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J-K input

EN input

Preset input (PRE)

Clear Input (CLR)

The voltage gain of the Inverting Amplifier is given by the relation ________

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Vout / Vin = - Rf / Ri

Vout / Rf = - Vin / Ri

Rf / Vin = - Ri / Vout

Rf / Vin = Ri / Vout

Stack is an acronym for_________

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FIFO memory

LIFO memory

Flash Memory

Bust Flash Memory

Caveman number system is Base ______ number system

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2

5

10

16

In the following statement Z PIN 20 ISTYPE „reg.invert‟; The keyword “reg.invert” indicates ________

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An inverted register input

An inverted register input at pin 20

Active-high Registered Mode output

Active-low Registered Mode output

The design and implementation of synchronous counters start from _________

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Truth table

k-map

state table

state diagram

THE GLITCHES DUE TO RACE CONDITION CAN BE AVOIDED BY USING A ___________

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GATED FLIP-FLOPS

PULSE TRIGGERED FLIP-FLOPS

POSITIVE-EDGE TRIGGERED FLIP-FLOPS

NEGATIVE-EDGE TRIGGERED FLIP-FLOPS

Consider A=1,B=0,C=1. A, B and C represent the input of three bit NAND gate the output of the NAND gate will be _____

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Zero

One

Undefined

No output as input is invalid

Which is not characteristic of a shift register?

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Serial in/parallel in

Serial in/parallel out

Parallel in/serial out

Parallel in/parallel out

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