Question # 1

The DMA controllers are special hardware embedded into the chip in modern integrate processor that __________ and ________ to the system.

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Data transfer

Arbitrate access

Both a and b

None

DI stand for

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Destination index

Defect index

Definition index

Delete index

Which system communicates with the outside word via the I/O devices interfaced to it.

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Microprocessor

Micro computer

Digital computer

All of these

The point where control returns after a subprogram is completed is known as the.

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Return address

Main address

Program address

Current address

Which Bus connects CPU and level 2 cache

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Rear side bus

Front side bus

Memory side bus

None

Which are the four categories of registers.

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General purpose register

Pointer or index registers

Segment registers

All of these

Alpha AXP is developed by

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DEC

IBM

Motorola

Intel

Power PC microprocessor architecture is developed by.

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Apple

IBM

Motorola

All these

Which bus plays a crucial role in I/O

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System bus

Control bus

address bus

Both a and b

Intel Used HMOS technology to recreate _____

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8084 A

8085 A

8086 A

8088 A

DIP stand for

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Deal inline package

Dual inline package

Direct inline package

Digital inline package

The ____________ was very successful in the calculator market at that time.

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Motorola 6800 and 6809

Microprocessor 4004

Intel 8085

None

Which formula is used to calculate the number of write stall cycles.

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Reads * read miss rate* read miss penalty

write * write miss + Write buffer stalls

Memory access* cache miss rate * cache miss penalty

None

How many bit or MAR register

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8 bit

16 bit

32 bit

64 bit

Which provided the current.

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Low cost

Slow cost

Low output

All of above

Which is not the control bus signal

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READ

WRITE

RESET

None

WB stand for

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Write buffers

Written buffers

Wrote buffers

None

Which is the small amount of highs speed memory used to work directly with the microprocessor

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Cache

Case

Cost

Coos

Motorola introduced 32 bit RISC processor called.

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MC 88100

MC 81100

MC 80100

MC 81000

Which formula is used to calculate the number of read stall cycles.

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Reads read miss rate read miss penalty

Write +Wrier buffer stalls

Memory access* cache miss rate * cache miss penalty

None

The capacity of this chip is 1 KB they are organized in the form of 1024 words with 8 bit word the what is the site of address bus.

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8 bit

10 bit

12 bit

16 bit

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