Question # 1

Which is the important part of a combinational logic block

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Index register

barrel shifter

Both a and b

None

Which is called super highway

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Processor

Multiplexer

Backbone bus

None

L2 cache memory is places at __________

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On processor

On mother board

On memory

All of these

LM stand for

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Least MAR

Load MAR

Least MRA

Load MRA

Which is the architecture of microprocessor.

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CISC

RISC

All of these

None

Motorola introduced 32 bit RISC processor called.

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MC 88100

MC 81100

MC 80100

MC 81000

AEN stand for

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Address enable

Address equivalent

Acknowledgment enable

Acknowledgment equivalent

RISC stand for.

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Reduced instruction set computer

Reduced instruct set compare

Reduce instruction stand computer

All of these

SP stand for

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Status pointer

Stack pointer

A and B

None

The mode of DMA are

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Single transfer

Transfer

Repeated Sigel transfer

All of these

Which register is connected to the memory by way of the address bus.

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MAR

MDR

SAM

None

The fetch execute cycle is to use a system know as.

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Assembly line

Pipelining

Cache

None

The time taken by the ADC from the active edge of SOC pulse till the active edge of EOC signal is called.

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Conversion over

Conversion delay

Conversion signal

None

Which year intel corporation introduced an updated version of the 8080-the 8085

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1965

1977

1976

1985

Which statement is false about WR signal

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WR signal controls the input buffer

the bar over Wr means that this is an active low signal

the bar over WR means that this is an active high signal

If WR is 0 then the input data reaches the latch input.

Which is the types of cache memory

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Fully associative cache

Direct mapped cache

Set associative cache

All of these

A microprocessor retries instructions from

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Control memory

Cache memory

Main memory

Virtual memory

When CS_ the chip is not selected at all hence D7 to D0 are driven to high impendence state.

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High

Low

Medium

Stand by

The lower red curvy arrow show that CPU places the address extracted from the memory location on the.

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Address bus

System bus

Control bus

Data bus

The ___________ of can assembly line to be 1/tp.

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Clock period

Pipelining

Through out

Flow thorugh

Which is the type of microcomputer memory

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Processor memory

Primary memory

Secondary memory

All of these

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PPSC Computer Science Chapter 17 Microprocessor And Assembly Language Online Test MCQs With Answers

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