Question # 1

_________ causes the address of the next microprocessor to be obtained from the memory.

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CRJA

ROM

MAP

HLT

The pin configuration of 8086 is available in the.

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40 pin

50 pin

30 pin

20 pin

EOC stand for

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End of conversion

Emphasize of conversion

End of controller

None

The beginning of very efficient ______ microprocessor in second generation.

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4-bit

8-bit

16 -bit

64 -bit

PA stand for

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Project address

Physical address

Pin address

Pointer address

The upper 8 bit are called.

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BH

AH

BL

DL

System bus contains

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Address bus

Data bus

Control bus

All of these

The principal of working of the cache memory largely depends on which locality.

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Spatial locality

Temporal locality

Sequentially

All of these

Which is the microprocessor launch by Fairchild company

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F-6

F-8

Both a and b

None

CISC stand for.

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Computer instruction system computer

Complex instruction set car

Complex instruction set computer

Resource instruction set computer

EB stand for

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Effect buffers

Effecting buffers

Effect ion buffers

Eviction buffers

How many architectural paradigms in microprocessor.

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2

3

4

6

MOC stand for

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Memory operation complex

Micro operation complex

Memory operation complete

None

A central processing unit fabricated on a single chip of semiconductor is called.

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RAM

ROM

Microprocessor

None

How many bit microprocessor developed by intel.

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4 bit

8 bit

32 bit

64 bit

T1 is the time taken for the stage and there are n stages in the.

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Through out

Assembly line

Both a and b

None

Which are the part of architecture of 8086

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The bus interface unit

The execution unit

Both a and b

None

How many bit or MAR register

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8 bit

16 bit

32 bit

64 bit

Which is the types of cache memory

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Fully associative cache

Direct mapped cache

Set associative cache

All of these

Which storage technique does not decoding circuit.

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Linear decoding

Fully decoding

partially

None

Which is not the main architectural feature of Power PC.

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It is not based on RISC

Superscalar implementation

Both 32 and 64 bit

Paged memory managemnet architecture

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